1. Field of the Invention
The invention relates generally to test methods, and more particularly to systems and methods for providing improved fault coverage of logic built-in-self-tests in integrated circuits by controlling the composition of the test input patterns.
2. Related Art
As digital devices (e.g., integrated circuits) have become more complex and more densely packed with logic gates and other electronic components, the need for effectively testing these devices has become more important. As the complexity of these devices increases, there are more and more opportunities for manufacturing defects to occur, thereby impairing or impeding the proper operation of the devices. The testing of these devices is becoming increasingly important. With respect to the testing of devices, and more particularly manufactured integrated circuits (ICs), one mechanism that is very useful is a built-in self test (BIST). This may also be referred to as a logic built-in self test (LBIST).
BIST and LBIST methodologies are generally considered part of a group of methodologies referred to as design-for-test (DFT) methodologies. DFT methodologies involve incorporating features into the actual designs of the circuits to facilitate testing of the circuits. BIST methodologies involve incorporating circuit components into the design of the circuit to be tested, where the additional circuit components are used for purposes of testing the functional portion of the circuitry.
In a typical LBIST system, LBIST circuitry within a device under test includes a plurality of scan chains interposed between levels of the functional logic of the device. Typically, pseudorandom patterns of bits are generated and stored in the scan chains. This may be referred to as scanning the data into the scan chains (during a scan shift phase). After a pseudorandom bit pattern is scanned into a scan chain, the data is propagated through the functional logic to a subsequent scan chain (during a functional phase). The data is then scanned out of the subsequent scan chain and compressed to reduce storage and bandwidth requirements, for example, through the use of a multiple input signature register, or MISR (during a scan shift phase) This test loop is typically repeated many times (e.g., 10,000 interations,) with the results of each test loop being combined in some manner with the results of the previous test loops. After all of the scheduled test loops have been completed, the final result is compared to a final result generated by a device that is known to operate properly operated in an identical test (using identical input data processed identically.) Based upon this comparison, it is determined whether the device under test operated properly.
Because the use of pseudorandom patterns is not deterministic (e.g., it does not test each and every possible combination of inputs, states and outputs), it does not provide the simple result that the logic circuit either does or does not have any defects. Instead, it provides a level of confidence that the logic circuit does or does not have defects. The greater the number of inputs and states that are tested (i.e., whose outputs are compared to expected values), the higher the confidence level that any defects have been identified by the testing. The number of random test patterns that are needed to achieve a particular level of confidence that the logic circuit contains no defects depends on the design of the logic circuit. This non-deterministic testing approach is typically easier and less expensive to implement than a deterministic approach.
In some conventional LBIST systems, the pseudorandom patterns may be weighted. Without weighting, the number of 1's in a random pattern is likely to be very nearly the same as the number of 0's. Weighting can be implemented in order to cause the generated pseudorandom pattern to have more 1's than 0's, or vice versa. For instance, it may be desirable to generate an input test pattern that has 30 percent 0's and 70 percent 1's. The weighted input test patterns may provide improved fault coverage in testing functional logic that may, during normal operation, have many inputs that are 1's (or many inputs that are 0's). If the coverage of each LBIST test can be improved, the amount of LBIST testing which needs to be performed to achieve a desired confidence level (that a device under test has no defects) can be reduced, thereby reducing test time and cost.
Conventionally, a single weighting value is applied to all of the pseudorandom input bit patterns. This weighting value (as well as the seed value for the pseudorandom pattern generator) is typically determined by empirical methods (e.g., trial and error). It would be desirable to provide improved systems and methods for determining optimal weighting for the pseudorandom bit patterns and optimal seed values. What defines optimal (i.e., best,) for a given device of use of a device, can vary. Means for determining optimal weighting would be even more desirable in an LBIST system (not known in the prior art) that utilizes different weighting values for one or more of the different channels (scan chains).